380 lines
7.7 KiB
C++
380 lines
7.7 KiB
C++
#ifndef __asm_math_H__
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#define __asm_math_H__
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#include "OgrePrerequisites.h"
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#define OGRE_COMPILER_MSVC -1
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC
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# pragma warning (push)
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// disable "instruction may be inaccurate on some Pentiums"
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# pragma warning (disable : 4725)
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#endif
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namespace Ogre
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{
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/*=============================================================================
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ASM math routines posted by davepermen et al on flipcode forums
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=============================================================================*/
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const float pi = 4.0f * atan( 1.0f );
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const float half_pi = 0.5f * pi;
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/*=============================================================================
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NO EXPLICIT RETURN REQUIRED FROM THESE METHODS!!
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=============================================================================*/
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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# pragma warning( push )
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# pragma warning( disable: 4035 )
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#endif
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float asm_arccos( float r ) {
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// return half_pi + arctan( r / -sqr( 1.f - r * r ) );
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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#error
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float asm_one = 1.f;
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float asm_half_pi = half_pi;
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__asm {
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fld r // r0 = r
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fld r // r1 = r0, r0 = r
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fmul r // r0 = r0 * r
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fsubr asm_one // r0 = r0 - 1.f
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fsqrt // r0 = sqrtf( r0 )
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fchs // r0 = - r0
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fdiv // r0 = r1 / r0
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fld1 // {{ r0 = atan( r0 )
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fpatan // }}
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fadd asm_half_pi // r0 = r0 + pi / 2
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} // returns r0
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#else
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return float( acos( r ) );
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#endif
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}
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float asm_arcsin( float r ) {
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// return arctan( r / sqr( 1.f - r * r ) );
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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const float asm_one = 1.f;
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__asm {
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fld r // r0 = r
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fld r // r1 = r0, r0 = r
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fmul r // r0 = r0 * r
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fsubr asm_one // r0 = r0 - 1.f
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fsqrt // r0 = sqrtf( r0 )
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fdiv // r0 = r1 / r0
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fld1 // {{ r0 = atan( r0 )
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fpatan // }}
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} // returns r0
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#else
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return float( asin( r ) );
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#endif
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}
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float asm_arctan( float r ) {
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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__asm {
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fld r // r0 = r
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fld1 // {{ r0 = atan( r0 )
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fpatan // }}
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} // returns r0
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#else
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return float( atan( r ) );
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#endif
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}
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float asm_sin( float r ) {
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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__asm {
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fld r // r0 = r
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fsin // r0 = sinf( r0 )
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} // returns r0
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#else
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return sin( r );
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#endif
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}
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float asm_cos( float r ) {
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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__asm {
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fld r // r0 = r
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fcos // r0 = cosf( r0 )
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} // returns r0
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#else
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return cos( r );
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#endif
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}
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float asm_tan( float r ) {
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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// return sin( r ) / cos( r );
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__asm {
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fld r // r0 = r
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fsin // r0 = sinf( r0 )
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fld r // r1 = r0, r0 = r
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fcos // r0 = cosf( r0 )
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fdiv // r0 = r1 / r0
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} // returns r0
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#else
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return tan( r );
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#endif
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}
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// returns a for a * a = r
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float asm_sqrt( float r )
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{
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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__asm {
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fld r // r0 = r
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fsqrt // r0 = sqrtf( r0 )
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} // returns r0
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#else
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return sqrt( r );
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#endif
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}
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// returns 1 / a for a * a = r
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// -- Use this for Vector normalisation!!!
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float asm_rsq( float r )
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{
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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__asm {
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fld1 // r0 = 1.f
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fld r // r1 = r0, r0 = r
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fsqrt // r0 = sqrtf( r0 )
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fdiv // r0 = r1 / r0
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} // returns r0
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#else
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return 1.0f / sqrt( r );
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#endif
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}
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// returns 1 / a for a * a = r
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// Another version
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float apx_rsq( float r ) {
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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const float asm_dot5 = 0.5f;
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const float asm_1dot5 = 1.5f;
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__asm {
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fld r // r0 = r
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fmul asm_dot5 // r0 = r0 * .5f
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mov eax, r // eax = r
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shr eax, 0x1 // eax = eax >> 1
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neg eax // eax = -eax
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add eax, 0x5F400000 // eax = eax & MAGICAL NUMBER
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mov r, eax // r = eax
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fmul r // r0 = r0 * r
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fmul r // r0 = r0 * r
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fsubr asm_1dot5 // r0 = 1.5f - r0
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fmul r // r0 = r0 * r
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} // returns r0
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#else
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return 1.0f / sqrt( r );
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#endif
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}
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/* very MS-specific, commented out for now
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Finally the best InvSqrt implementation?
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Use for vector normalisation instead of 1/length() * x,y,z
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*/
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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__declspec(naked) float __fastcall InvSqrt(float fValue)
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{
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__asm
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{
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mov eax, 0be6eb508h
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mov dword ptr[esp-12],03fc00000h
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sub eax, dword ptr[esp + 4]
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sub dword ptr[esp+4], 800000h
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shr eax, 1
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mov dword ptr[esp - 8], eax
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fld dword ptr[esp - 8]
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fmul st, st
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fld dword ptr[esp - 8]
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fxch st(1)
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fmul dword ptr[esp + 4]
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fld dword ptr[esp - 12]
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fld st(0)
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fsub st,st(2)
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fld st(1)
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fxch st(1)
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fmul st(3),st
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fmul st(3),st
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fmulp st(4),st
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fsub st,st(2)
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fmul st(2),st
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fmul st(3),st
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fmulp st(2),st
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fxch st(1)
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fsubp st(1),st
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fmulp st(1), st
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ret 4
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}
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}
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#endif
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// returns a random number
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FORCEINLINE float asm_rand()
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{
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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#if 0
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#if OGRE_COMP_VER >= 1300
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static unsigned __int64 q = time( NULL );
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_asm {
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movq mm0, q
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// do the magic MMX thing
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pshufw mm1, mm0, 0x1E
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paddd mm0, mm1
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// move to integer memory location and free MMX
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movq q, mm0
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emms
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}
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return float( q );
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#endif
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#else
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// VC6 does not support pshufw
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return float( rand() );
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#endif
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#else
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// GCC etc
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return float( rand() );
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#endif
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}
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// returns the maximum random number
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FORCEINLINE float asm_rand_max()
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{
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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#if 0
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#if OGRE_COMP_VER >= 1300
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return (std::numeric_limits< unsigned __int64 >::max)();
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return 9223372036854775807.0f;
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#endif
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#else
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// VC6 does not support unsigned __int64
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return float( RAND_MAX );
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#endif
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#else
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// GCC etc
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return float( RAND_MAX );
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#endif
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}
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// returns log2( r ) / log2( e )
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float asm_ln( float r ) {
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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const float asm_1_div_log2_e = .693147180559f;
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const float asm_neg1_div_3 = -.33333333333333333333333333333f;
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const float asm_neg2_div_3 = -.66666666666666666666666666667f;
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const float asm_2 = 2.f;
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int log_2 = 0;
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__asm {
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// log_2 = ( ( r >> 0x17 ) & 0xFF ) - 0x80;
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mov eax, r
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sar eax, 0x17
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and eax, 0xFF
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sub eax, 0x80
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mov log_2, eax
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// r = ( r & 0x807fffff ) + 0x3f800000;
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mov ebx, r
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and ebx, 0x807FFFFF
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add ebx, 0x3F800000
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mov r, ebx
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// r = ( asm_neg1_div_3 * r + asm_2 ) * r + asm_neg2_div_3; // (1)
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fld r
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fmul asm_neg1_div_3
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fadd asm_2
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fmul r
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fadd asm_neg2_div_3
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fild log_2
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fadd
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fmul asm_1_div_log2_e
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}
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#else
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return log( r );
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#endif
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}
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC && OGRE_ARCH_TYPE == OGRE_ARCHITECTURE_32
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# pragma warning( pop )
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#endif
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} // namespace
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#if OGRE_COMPILER == OGRE_COMPILER_MSVC
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# pragma warning (pop)
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#endif
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#endif
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