103 lines
3.6 KiB
HTML
103 lines
3.6 KiB
HTML
<p>Note that this package supports syntax highlighting for both Verilog and System Verilog.</p>
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<h2>Comments</h2>
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<pre><code>/* Multiline comments in Verilog
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look like C comments and // is OK in here. */
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// Single-line comment in Verilog.</code></pre>
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<h2>Literals</h2>
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<pre><code>// example code from: http://iroi.seu.edu.cn/books/asics/Book2/CH11/CH11.02.htm
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module declarations;
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parameter H12_UNSIZED = 'h 12;
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parameter H12_SIZED = 6'h 12;
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parameter D42 = 8'B0010_1010;
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parameter D123 = 123;
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parameter D63 = 8'o 77;
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parameter A = 'h x, B = 'o x, C = 8'b x, D = 'h z, E = 16'h ????;
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reg [3:0] B0011,Bxxx1,Bzzz1;
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real R1,R2,R3;
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integer I1,I3,I_3;
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parameter BXZ = 8'b1x0x1z0z;
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initial begin
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B0011 = 4'b11; Bxxx1 = 4'bx1; Bzzz1 = 4'bz1;
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R1 = 0.1e1; R2 = 2.0; R3 = 30E-01;
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I1 = 1.1; I3 = 2.5; I_3 = -2.5;
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end
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initial begin #1;
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$display("H12_UNSIZED, H12_SIZED (hex) = %h, %h",H12_UNSIZED, H12_SIZED);
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$display("D42 (bin) = %b",D42," (dec) = %d",D42);
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$display("D123 (hex) = %h",D123," (dec) = %d",D123);
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$display("D63 (oct) = %o",D63);
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$display("A (hex) = %h",A," B (hex) = %h",B);
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$display("C (hex) = %h",C," D (hex) = %h",D," E (hex) = %h",E);
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$display("BXZ (bin) = %b",BXZ," (hex) = %h",BXZ);
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$display("B0011, Bxxx1, Bzzz1 (bin) = %b, %b, %b",B0011,Bxxx1,Bzzz1);
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$display("R1, R2, R3 (e, f, g) = %e, %f, %g", R1, R2, R3);
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$display("I1, I3, I_3 (d) = %d, %d, %d", I1, I3, I_3);
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end
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endmodule</code></pre>
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<h2>Full example</h2>
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<pre><code>`include "internal_defines.vh"
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//*****************************************************************************
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// memory_decoder: a custom module used to handle memory transactions
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//*****************************************************************************
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//
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// out_mem (output) - The output to memory
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// out_reg (output) - The output to the register file
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// mem_we (output) - Which byte in the word to write too
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// mem_in (input) - The input from memory
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// addr_in (input) - The lowest 2 bits of byte offset to store in memory
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// data_in (input) - The input from the register file to be stored
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// l_bit (input) - The load bit signal (control)
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// b_bit (input) - The byte bit signal (control)
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//
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module memory_decoder(out_mem, out_reg, mem_in, data_in, l_bit, b_bit, addr_in,
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mem_we);
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output reg [31:0] out_mem, out_reg;
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output reg [3:0] mem_we;
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input [31:0] mem_in, data_in;
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input [1:0] addr_in;
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input l_bit, b_bit;
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always_comb begin
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mem_we = 4'b0000; // dont write memory by default
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if (l_bit == 1) begin // ldr and ldrb
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out_mem = mem_in; // dont change memory!
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if (b_bit == 1) begin
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/* figure out which byte to load from memory */
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case (addr_in)
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2'b00: out_reg = {24'b00, mem_in[7:0]};
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2'b01: out_reg = {24'b00, mem_in[15:8]};
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2'b10: out_reg = {24'b00, mem_in[23:16]};
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2'b11: out_reg = {24'b00, mem_in[31:24]};
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endcase
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end
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else begin
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out_reg = mem_in;
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end
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end
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else begin // str and strb
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out_reg = `UNKNOWN; // We are not reading from mem
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if (b_bit == 1) begin
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/* figure out which byte to write to in memory */
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out_mem = {4{data_in[7:0]}};
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case (addr_in)
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2'b00: mem_we = 4'b1000;
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2'b01: mem_we = 4'b0100;
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2'b10: mem_we = 4'b0010;
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2'b11: mem_we = 4'b0001;
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endcase
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end
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else begin
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mem_we = 4'b1111; // write to all channels
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out_mem = data_in;
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end
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end
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end
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endmodule</code></pre> |