93 lines
2.9 KiB
HTML
93 lines
2.9 KiB
HTML
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<h2>Comments</h2>
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<pre><code>-- I am a comment
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I am not</code></pre>
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<h2>Literals</h2>
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<pre><code>constant FREEZE : integer := 32;
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constant TEMP : real := 32.0;
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A_INT <= 16#FF#;
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B_INT <= 2#1010_1010#;
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MONEY := 1_000_000.0;
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FACTOR := 2.2E-6;
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constant DEL1 :time := 10 ns;
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constant DEL2 :time := 2.27 us;
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type MY_LOGIC is ('X','0','1','Z');
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type T_STATE is (IDLE, READ, END_CYC);
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signal CLK : MY_LOGIC := '0';
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signal STATE : T_STATE := IDLE;
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constant FLAG :bit_vector(0 to 7) := "11111111";
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constant MSG : string := "Hello";
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BIT_8_BUS <= B"1111_1111";
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BIT_9_BUS <= O"353";
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BIT_16_BUS <= X"AA55";
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constant TWO_LINE_MSG : string := "Hello" & CR & "World";</code></pre>
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<h2>Full example</h2>
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<pre><code>-- example code from: http://www.csee.umbc.edu/portal/help/VHDL/samples/samples.html
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity fadd is -- full adder stage, interface
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port(a : in std_logic;
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b : in std_logic;
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cin : in std_logic;
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s : out std_logic;
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cout : out std_logic);
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end entity fadd;
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architecture circuits of fadd is -- full adder stage, body
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begin -- circuits of fadd
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s <= a xor b xor cin after 1 ns;
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cout <= (a and b) or (a and cin) or (b and cin) after 1 ns;
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end architecture circuits; -- of fadd
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity add32 is -- simple 32 bit ripple carry adder
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port(a : in std_logic_vector(31 downto 0);
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b : in std_logic_vector(31 downto 0);
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cin : in std_logic;
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sum : out std_logic_vector(31 downto 0);
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cout : out std_logic);
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end entity add32;
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architecture circuits of add32 is
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signal c : std_logic_vector(0 to 30); -- internal carry signals
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begin -- circuits of add32
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a0: entity WORK.fadd port map(a(0), b(0), cin, sum(0), c(0));
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stage: for I in 1 to 30 generate
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as: entity WORK.fadd port map(a(I), b(I), c(I-1) , sum(I), c(I));
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end generate stage;
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a31: entity WORK.fadd port map(a(31), b(31), c(30) , sum(31), cout);
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end architecture circuits; -- of add32
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use STD.textio.all;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_textio.all;
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entity signal_trace is
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end signal_trace;
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architecture circuits of signal_trace is
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signal a: std_logic_vector(31 downto 0) := x"00000000";
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signal b: std_logic_vector(31 downto 0) := x"FFFFFFFF";
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signal cin: std_logic := '1';
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signal cout: std_logic;
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signal sum: std_logic_vector(31 downto 0);
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begin -- circuits of signal_trace
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adder: entity WORK.add32 port map(a, b, cin, sum, cout); -- parallel circuit
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prtsum: process (sum)
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variable my_line : LINE;
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alias swrite is write [line, string, side, width] ;
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begin
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swrite(my_line, "sum=");
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write(my_line, sum);
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swrite(my_line, ", at=");
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write(my_line, now);
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writeline(output, my_line);
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end process prtsum;
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end architecture circuits; -- of signal_trace</code></pre>
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